As disclosed in Japanese Patent Laid-Open No. 59-173839, there is a technology for an information processing apparatus including an external device controller in which when an external device is connected to the information processing apparatus so as to be capable of communicating therewith, an operation clock is supplied from the external device controller of the information processing apparatus to the external device. Here, generally, the external device is set so as to output data in synchronization with the clock supplied from the external device controller, and the external device controller is configured to load therein the data output from the external device.
With the use of this method, the external device controller temporarily stops supply of clocks (corresponding to clock gating) to the external device, thus allowing the supply of data from the external device to the external device controller to be temporarily stopped. For example, when data is accumulated up to the allowed capacity of a reception buffer in the external device controller, the external device controller can stop supply of clocks to stop supply of data, thus preventing an overflow of the buffer as desired even if the capacity of the buffer is small.
When data received by an external device controller from an external device is delayed by one cycle or more with respect to the output clock of the external device controller, failure to load data occurs because a control signal for stopping clock supply to the external device is used in the external device controller directly for control in which reception of data from the external device is stopped.
In addition, if the timing at which the external device controller is caused to stop (or cancel stopping of) loading data therein is to be adjusted, the time required for the adjustment process is long.